Ren Chen
Ph.D of Electrical Engineering, University of Southern California
Parallel Computing, Graph Analytics, Machine Learning

About Research Interests

  • Parallel Computing and Hetergoneous Computing using Multi-Core, GPUs, and FPGAs
  • Largeg Scale Graph Analytics and Computing, and Parallel Graph Algorithms
  • Large Scale Machine Learning on Distributed Machines

About Research Experience

  • Research Assistant at University of Southern California (USC), USA, Sep. 2012-Present
    • Optimized throughput and energy performance of database operations on FPGA
    • Developed automatic generation tool of linear transform algorithms on FPGA
    • Developed algorithmic optimizations for realizing data intensive applications on 3D Memory integrated FPGA
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  • Research Assistant at University of Southeast University (SEU), China, Sep.2010-May 2012
    • Conducted research on model-based design space exploration for high performance coarse grained reconfigurable array (CGRA) design
    • Researched on software pipeline based automatic algorithm mapping technique on CGRA
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  • Research internship at Tsing Hua University, China, Mar. 2010-Sep. 2010
    • Microelectronics Lab
    • Focused on compiler for Processing Element Arrays
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  • Research internship at Southeast University (SEU), China, Oct. 2009-Aug.2010
    • Developed a CGRA simulator integrating SimpleScalar through transaction-level modeling
    • Implemented a C++ based CGRA compiler back end
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List of Publications

Graph Computing and Analytics

  • [Full Paper] Qingsong Wen, Ren Chen, Lifeng Nai, Li Zhou and Yinglong Xia, Finding top K shortest simple paths with improved space efficiency, ACM SIGMOD/PODS Workshop on Graph Data-management Experiences and Systems (GRADES 2017), Chicago, IL, May 2017.
  • [Full Paper] Q. Wen, R. Chen, Y. Xia, L. Zhou, J. Deng, J. Xu, and M. Xia, Big-Data helps SDN to verify integrity of control/data planes, in Big-Data and Software Defined Networking, IET Book Series on Big Data, Sep. 2017
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Database Acceleration by CPU and FPGA

  • [Full Paper] Ren Chen and Viktor K. Prasanna, Acclerating Equi-Join on a CPU-FPGA Heterogeneous Platform, IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM '16, Acceptance rate: 19%), March 2016
  • [Full Paper] Ajitesh Srivastava, Ren Chen and Viktor K. Prasanna, A Hybrid Design for High Performance Large-scale Sorting on FPGA, IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig '15), December 2015
  • [Full Paper] Chi Zhang, Ren Chen and Viktor K. Prasanna, High Throughput Large Scale Sorting on a CPU-FPGA Heterogeneous Platform, 23nd Reconfigurable Architectures Workshop (RAW), 30th Annual International Parallel & Distributed Processing Symposium (IPDPS), Feb 2016.(IPDPS RAW '15, Best Paper Candidate)
  • [Full Paper] Ren Chen and Viktor K. Prasanna, Energy and Memory Efficient Bitonic Sorting on FPGA, ACM/SIGDA International Conference on Field-Programmable Gate Arrays (FPGA '15, Acceptance rate: 20.6%), February 2015
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Parallel Algorithm

  • [Full Paper] Ren Chen and Viktor K. Prasanna, Automatic Generation of High Throughput Energy Efficient Architectures for Permutation on Streaming Data, IEEE International Conference on Field Programmable Logic and Applications (FPL '15, Acceptance ratio: 24%)
  • [Poster] Ren Chen and Viktor K. Prasanna, Energy-Efficient Architecture for Permutation on Streaming Data, Ph.D forum on IEEE Parallel & Distributed Processing Symposium (IPDPS '14)
  • [Full Paper] Ren Chen and Viktor K. Prasanna, Energy-Efficient Architecture for Stride Permutation on Streaming Data, IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig '13, Acceptance ratio: 35.2%), December 2013
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System Architecture and Memory

  • [Full Paper] Ren Chen, Shreyas Singapura and Viktor K. Prasanna, Optimal Dynamic Data Layouts for 2D FFT on 3D Memory Integrated FPGA, Journal of Supercomputing (SUPE), March 2016
  • [Full Paper] Ren Chen, Shreyas Singapura and Viktor K. Prasanna, Optimal Dynamic Data Layouts for 2D FFT on 3D Memory Integrated FPGA, International Conference on Parallel Computing Technologies (PaCT '15)
  • [Short Paper] Ren Chen and Viktor K. Prasanna, DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-based Systems, 11th International Symposium on Applied Reconfigurable Computing (ARC '15), Best poster award (top 5 among 30 posters), April 2015
  • [Full Paper] Sanmukh R. Kuppannagari, Shreyas G. Singapura, Ren Chen, Andrea Sanny, Geoffrey Phi C. Tran, Shijie Zhou, Yusong Hu, Stephen P. Crago, Viktor K. Prasanna, Energy Performance of FPGAs on PERFECT Suite Kernels, IEEE 18th International Conference on High Performance Extreme Computing (HPEC '14), September 2014
  • [Full Paper] Ren Chen, Lu Ma, Du Yue, Wen Wen, Zhi Qi, Hierarchy Modeling and Co-simulation of a Dynamically Coarse-Grained Reconfigurable Architecture, Informatics in Control, Automation and Robotics. Springer Berlin Heidelberg, 2012. 589-598.
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Signal and Image Processing

  • [Full Paper] Ren Chen and Viktor K. Prasanna, Optimal Circuits for Parallel Bit Reversal, ACM/SIGDA Design Automation Conference (DAC '17)
  • [Full Paper] Ren Chen and Viktor K. Prasanna, Optimizing interconnection complexity for realizing fixed permutation in data and signal processing algorithms, IEEE International Conference on Field Programmable Logic and Applications (FPL '16, Acceptance ratio: 22%)
  • [Full Paper] Ren Chen and Viktor K. Prasanna, Energy Optimizations for FPGA-based 2-D FFT architecture, IEEE 18th International Conference on High Performance Extreme Computing (HPEC '14), September 2014
  • [Short Paper] Ren Chen and Viktor K. Prasanna, Algorithmic Optimizations for Energy-efficient Throughput-oriented FFT architecture, IEEE Green Computing Conference (IGCC '14), November 2014
  • [Full Paper] Ren Chen, Neungsoo Park and and Viktor K. Prasanna, High Throughput Energy Efficient Parallel FFT Architecture on FPGAs, IEEE High Performance Extreme Computing Conference (HPEC '13), September 2013
  • [Full Paper] Ren Chen, Hoang Le and Viktor K. Prasanna, Energy Efficient Parameterized FFT Architecture, IEEE International Conference on Field Programmable Logic and Applications (FPL '13, Acceptance ratio: 23%), August 2013
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About Research Activities

  • Paper reviewer for IEEE Conference on Field-Programmable Custom Computing Machines (FCCM)
  • Paper reviewer for IEEE Conference on ReConFigurable Computing and FPGAs (ReConFig)
  • Paper reviewer for IEEE Conference on High Performance Extreme Computing (HPEC)
  • Paper reviewer for IEEE Conference on ParaFPGA
  • Coordinator of Parallel Computing Group at USC
  • Poster presenter in the Ming Hsieh Institue Research Festival 2013 at USC

About Research Affilications

  • ACM Graduate Student Member
  • IEEE Graduate Student Member, California Region
  • Proceeding Chair of HiPC, 2016

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